MC68HC05V12 Datasheet, PDF (62/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Interrupts
Freescale Semiconductor, Inc.
these features permit the safe use of read-modify-write instructions (for
instance, BSET and BCLR) on the ISCR.
NOTE:
Although read-modify-write instruction use is allowable on the ISCR,
shift operations should be avoided due to the possibility of inadvertently
setting the IRQA.
4.7.1 IRQ Status and Control Register
The IRQ interrupt function is controlled by the IRQ status and control
register (ISCR) located at $001F. All unused bits in the ISCR will read as
logic 0s. The IRQF bit is cleared and IRQE bit is set by reset.
Address: $001F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
IRQF
0
IPCF
0
IRQE
IPCE
Write:
IRQA
Reset: 1
0
0
0
0
0
0
0
= Unimplemented
Figure 4-3. IRQ Status and Control Register (ISCR)
IRQE — IRQ Interrupt Enable Bit
The IRQE bit controls whether the IRQF flag bit can or cannot initiate
an IRQ interrupt sequence. If the IRQE enable bit is set, the IRQF flag
bit can generate an interrupt sequence. If the IRQE enable bit is
cleared, the IRQF flag bit cannot generate an interrupt sequence.
Reset sets the IRQE enable bit, thereby enabling IRQ interrupts once
the I bit is cleared. Execution of the STOP or WAIT instructions
causes the IRQE bit to be set to allow the external IRQ to exit these
modes. In addition, reset also sets the I bit, which masks all interrupt
sources.
IPCE — Port C IRQ Interrupt Enable Bit
The IPCE bit controls whether the IPCF flag bit can or cannot initiate
an IRQ interrupt sequence. If the IPCE enable bit is set, the IPCF flag
bit will generate an interrupt sequence. If the IPCE enable bit is
cleared, the IPCF flag bit will not generate an interrupt sequence.
Technical Data
Interrupts
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MC68HC05V12 — Rev. 2.0