MC68HC05V12 Datasheet, PDF (57/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Interrupts
CPU Interrupt Processing
When an interrupt is to be processed, the CPU fetches the address of
the appropriate interrupt software service routine from the vector table at
locations $3FF0–$3FFF as defined in Table 4-1.
Table 4-1. Vector Address for Interrupts and Reset
Register Flag Name
Interrupts
N/A
N/A
ISCR
TSR
TSR
TSR
BSVR
SPSR
CTSCR
CTSCR
SSCR
N/A
Reset
N/A
Software
IRQF/IPCF
External
(IRQ and port C)
TOF
Timer overflow
OCF
Output compare
ICF
Input capture
I3:I0
BDLC
SPIF
SPI
CTOF Core timer overflow
RTIF
Real time
SYNF Gauge synchronize
CPU
Interrupt
RESET
SWI
IRQ
TIMER
TIMER
TIMER
BDLC
SPI
CTIMER
CTIMER
GAUGE
Vector
Address
$3FFE–$3FFF
$3FFC–$3FFD
$3FFA–$3FFB
$3FF8–$3FF9
$3FF8–$3FF9
$3FF8–$3FF9
$3FF6–$3FF7
$3FF4–$3FF5
$3FF2–$3FF3
$3FF2–$3FF3
$3FF0–$3FF1
Because the M68HC05 CPU does not support interruptible instructions,
the maximum latency to the first instruction of the interrupt service
routine must include the longest instruction execution time plus stacking
overhead.
Latency = (Longest instruction execution time + 10) x t_CYC seconds
A return-from-interrupt (RTI) instruction is used to signify when the
interrupt software service routine is completed. The RTI instruction
causes the register contents to be recovered from the stack and normal
processing to resume at the next instruction that was to be executed
when the interrupt took place. Figure 4-1 shows the sequence of events
that occur during interrupt processing.
MC68HC05V12 — Rev. 2.0
Interrupts
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Technical Data