MC68HC05V12 Datasheet, PDF (73/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Resets
Internal Resets
5.4.3 Illegal Address Reset
An illegal address reset is generated when the CPU attempts to fetch an
instruction from either unimplemented address space ($01C0 to $023F
and $0340 to $0CFF) or input/output (I/O) address space ($0000 to
$003F).
The illegal address reset will activate the internal pulldown device
connected to the RESET pin.
5.4.4 Disabled STOP Instruction Reset
When the mask option is selected to disable the STOP instruction,
execution of a STOP instruction results in an internal reset. This
activates the internal pulldown device connected to the RESET pin.
5.4.5 Low-Voltage Reset (LVR)
The internal low-voltage reset (LVR) is generated when V_DD falls below
the LVR threshold, V_LVRI, and will be released following a POR delay
starting when V_DD rises above V_LVRR. The LVR threshold is tested to be
above the minimum operating voltage of the microcontroller and is
intended to assure that the CPU will be held in reset when the V_DD
supply voltage is below reasonable operating limits. A mask option is
provided to disable the LVR when the device is expected to normally
operate at low voltages. Note that the V_DD rise and fall slew rates
(S_VDDR and S_VDDF) must be within the specification for proper LVR
operation. If the specification is not met, the circuit will operate properly
following a delay of V_DD/slew rate.
The LVR will generate the RST signal which will reset the CPU and other
peripherals. The low-voltage reset will activate the internal pulldown
device connected to the RESET pin.
If any other reset function is active at the end of the LVR reset signal, the
RST signal will remain in the reset condition until the other reset
condition(s) end.
MC68HC05V12 — Rev. 2.0
Resets
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