MC68HC05V12 Datasheet, PDF(161/246 Page) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

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MC68HC05V12 Datasheet, PDF (161/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

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Freescale Semiconductor, Inc.

Byte Data Link Controller â Digital (BDLCâD)

BDLC Protocol Handler

In any case, if the bus fault is temporary, as soon as the fault is

cleared, the BDLC will resume normal operation. If the bus fault is

permanent, it may result in permanent loss of communication on the

J1850 bus. See 14.7.4 BDLC State Vector Register.

BREAK â Break

If a BREAK symbol is received while the BDLC is transmitting or

receiving, an invalid symbol (in BSVR) interrupt will be generated.

Reading the BSVR (see 14.7.4 BDLC State Vector Register) will

clear this interrupt condition. The BDLC will wait for the bus to idle,

then wait for a start-of-frame (SOF) symbol.

The BDLC cannot transmit a BREAK symbol. It only can receive a

BREAK symbol from the J1850 bus.

14.6.5.5 Summary

Table 14-1. BDLC J1850 Bus Error Summary

Error Condition

Transmission error

Cyclical redundancy check (CRC) error

Invalid symbol: BDLC transmits, but

receives invalid bits (noise)

Framing error

Bus short to VDD

Bus short to GND

BDLC receives BREAK symbol

BDLC Function

For invalid bits or framing symbols on non-byte boundaries, invalid

symbol interrupt will be generated. BDLC stops transmission.

CRC error interrupt will be generated. The BDLC will wait for EOF.

The BDLC will abort transmission immediately. Invalid symbol

interrupt will be generated.

Invalid symbol interrupt will be generated. The BDLC will wait for end

of frame (EOF).

The BDLC will not transmit until the bus is idle. Invalid symbol

interrupt will be generated. EOF interrupt also must be seen

before another transmission attempt. Depending on length of the

short, LOA ï¬ag also may be set.

Thermal overload will shut down physical interface. Fault condition is

seen as invalid symbol ï¬ag. EOF interrupt must also be seen

before another transmission attempt.

Invalid symbol interrupt will be generated. The BDLC will wait for the

next valid SOF.

MC68HC05V12 â Rev. 2.0

Byte Data Link Controller â Digital (BDLCâD)

For More Information On This Product,

Go to: www.freescale.com

Technical Data

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