MC68HC05V12 Datasheet, PDF (162/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital
14.7 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the
BDLC and consists of five user registers.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 14-15. BDLC Block Diagram
Technical Data
Byte Data Link Controller – Digital (BDLC–D)
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MC68HC05V12 — Rev. 2.0