MC68HC05V12 Datasheet, PDF (90/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Core Timer
Freescale Semiconductor, Inc.
TOFE — Timer Overflow Enable Bit
When this bit is set, a CPU interrupt request is generated when the
CTOF bit is set. Reset clears this bit.
RTIE — Real-Time Interrupt Enable Bit
When this bit is set, a CPU interrupt request is generated when the
RTIF bit is set. Reset clears this bit.
TOFC — Timer Overflow Flag Clear Bit
When a 1 is written to this bit, CTOF is cleared. Writing a 0 has no
effect on the CTOF bit. This bit always reads as 0.
RTFC — Real-Time Interrupt Flag Clear Bit
When a 1 is written to this bit, RTIF is cleared. Writing a 0 has no
effect on the RTIF bit. This bit always reads as 0.
RT1–RT0 — Real-Time Interrupt Rate Select Bits
These two bits select one of four taps from the real-time interrupt
circuit. See Table 8-1 which shows the available interrupt rates with
a 2.1- and 1.05-MHz bus clock. Reset sets bits RT1 and RT0, which
selects the lowest periodic rate, and gives the maximum time in which
to alter these bits if necessary. Take care when altering RT0 and RT1
if the timeout period is imminent or uncertain. If the selected tap is
modified during a cycle in which the counter is switching, an RTIF
could be missed or an additional one could be generated. To avoid
problems, the COP should be cleared before changing RTI taps.
Table 8-1. RTI and COP Rates at 2.1 MHz
RTI Rate
2.1 MHz 1.05 MHz
RT1–RT0
Minimum COP Rates
2.1 MHz 1.05 MHz
0.97 ms 1.95 ms ₂¹¹_/E
00
(2¹⁴–2¹¹)/E ^{6.83 ms 13.65 ms}
1.95 ms 3.90 ms ₂¹²_/E
01
(2¹⁵–2¹²)/E ^{13.65 ms 27.31 ms}
3.90 ms 7.80 ms ₂¹³_/E
10
(2¹⁶–2¹³)/E ^{27.31 ms 54.61 ms}
7.80 ms 15.60 ms ₂¹⁴_/E
11
(2¹⁷–2¹⁴)/E ^{54.61 ms 109.23 ms}
Technical Data
Core Timer
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MC68HC05V12 — Rev. 2.0