MC68HC05V12 Datasheet, PDF (140/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital
14.4.1.4 BDLC Wait Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and if the WCM bit in
the BCR1 register is cleared previously.
In this mode, the BDLC internal clocks continue to run. The first passive-
to-active transition of the bus generates a CPU interrupt request from the
BDLC, which wakes up the BDLC and the CPU. In addition, if the BDLC
receives a valid end-of-frame (EOF) symbol while operating in wait
mode, then the BDLC also will generate a CPU interrupt request, which
wakes up the BDLC and the CPU. See 14.8.1 Wait Mode.
14.4.1.5 BDLC Stop Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BCR1 is set previously.
In this mode, the BDLC internal clocks are stopped but the physical
interface circuitry is placed in a low-power mode and awaits network
activity. If network activity is sensed, then a CPU interrupt request will be
generated, restarting the BDLC internal clocks. See 14.8.2 Stop Mode.
14.4.1.6 Digital Loopback Mode
When a bus fault has been detected, the digital loopback mode is used
to determine if the fault condition is caused by failure in the node’s
internal circuits or elsewhere in the network, including the node’s analog
physical interface. In this mode, the transmit digital output pin (BDTxD)
and the receive digital input pin (BDRxD) of the digital interface are
disconnected from the analog physical interface and tied together to
allow the digital portion of the BDLC to transmit and receive its own
messages without driving the J1850 bus.
Technical Data
Byte Data Link Controller – Digital (BDLC–D)
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MC68HC05V12 — Rev. 2.0