MC68HC05V12 Datasheet, PDF (119/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Pulse Width Modulators (PWMs)
PWM Registers
11.4.3 PWMA Data Register
The PWMA system has one 6-bit data register which holds the duty
cycle information. The data bits in this register are unaffected by reset.
A value of $00 in this register corresponds to a steady state output level
(0 percent duty cycle) on the PWMA pin. The logic level of the output will
depend on the value of the POLA bit in the PWMA control register.
Address: $0036
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
POLA
Write:
D5
D4
D3
D2
D1
D0
Reset: 0
0
U
U
U
U
U
U
= Unimplemented U = Unaffected
Figure 11-7. PWMA Data Register (PWMAD)
POLA — PWMA Polarity Bits
1 = PWMA pulse is active high.
0 = PWMA pulse is active low.
11.4.4 PWMB Data Register
The PWMB system has one 6-bit data register which holds the duty
cycle information. These bits work the same way as the data bits in the
PWMA data register except they affect the PWMB output pin. The data
bits in this register are unaffected by reset.
Address: $0038
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
POLB
Write:
D5
D4
D3
D2
D1
D0
Reset: 0
0
U
U
U
U
U
U
= Unimplemented U = Unaffected
Figure 11-8. PWMB Data Register (PWMBD)
POLB — PWMB Polarity Bit
1 = PWMB pulse is active high.
0 = PWMB pulse is active low.
MC68HC05V12 — Rev. 2.0
Pulse Width Modulators (PWMs)
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Technical Data