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MC68HC05V12 Datasheet, PDF (71/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit
Freescale Semiconductor, Inc.
Resets
Internal Resets
5.4.2.1 Resetting the COP
Preventing a COP reset is done by writing a 0 to the COPR bit. This
action will reset the counter and begin the timeout period again. The
COPR bit is bit 0 of address $3FF0. A read of address $3FF0 will return
user data programmed at that location.
5.4.2.2 COP during Wait Mode
The COP will continue to operate normally during wait mode. The
system should be configured to pull the device out of wait mode
periodically and reset the COP by writing to the COPR bit to prevent a
COP reset.
5.4.2.3 COP during Stop Mode
When the STOP enable mask option is selected, stop mode disables the
oscillator circuit and thereby turns the clock off for the entire device. The
COP counter will be reset when stop mode is entered. If a reset is used
to exit stop mode, the COP counter will be held in reset during the 4064
cycles of startup delay. If any operable interrupt is used to exit stop
mode, the COP counter will not be reset during the 4064-cycle startup
delay and will have that many cycles already counted when control is
returned to the program.
5.4.2.4 COP Watchdog Timer Considerations
The COP watchdog timer is active in user mode if enabled by the COP
mask option. If the COP watchdog timer is selected, any execution of the
STOP instruction (either intentional or inadvertent due to the CPU being
disturbed) will cause the oscillator to halt and prevent the COP watchdog
timer from timing out. Therefore, it is recommended that the STOP
instruction should be disabled if the COP watchdog timer is enabled.
If the COP watchdog timer is selected, the COP will reset the MCU when
it times out. Therefore, it is recommended that the COP watchdog
should be disabled for a system that must have intentional uses of the
wait mode for periods longer than the COP timeout period.
MC68HC05V12 — Rev. 2.0
Resets
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Technical Data