MC68HC05V12 Datasheet, PDF (70/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Resets
Freescale Semiconductor, Inc.
VDD
0V
OSC12
INTERNAL
PROCESSOR
CLOCK1
INTERNAL
ADDRESS
BUS1
INTERNAL
DATA
BUS ¹
4064 tcyc
tcyc
3FFE 3FFF NEW PC NEW PC
NEW NEW
PCH PCL
OP
CODE
RESET
3FFE 3FFE 3FFE 3FFE 3FFF NEW PC NEW PC
PCH PCL
OP
CODE
tRL
3
Notes:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
Figure 5-2. RESET and POR Timing Diagram
5.4.2 Computer Operating Properly Reset (COPR)
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to time out, an internal reset is
generated to reset the MCU. Regardless of an internal or external reset,
the MCU comes out of a COP reset according to the pin conditions that
determine mode selection.
The COP reset function is enabled or disabled by the COP mask option.
The COP watchdog reset will activate the internal pulldown device
connected to the RESET pin.
Technical Data
Resets
For More Information On This Product,
Go to: www.freescale.com
MC68HC05V12 — Rev. 2.0