MC68HC05V12 Datasheet, PDF (103/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SPI Signal Description
SS
SCK
(CPOL = 0,
CPHA = 0)
SCK
(CPOL = 0,
CPHA = 1)
SCK
(CPOL = 1,
CPHA = 0)
SCK
(CPOL = 1,
CPHA = 1)
MISO/MOSI
MSB
6
5
4
3
2
1
0
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
Figure 10-1. Data Clock Timing Diagram
10.4.1 Slave Select (SS/PB0)
The slave select (SS) pin is used to select the MCU as a slave device. It
has to be low prior to data transactions and must stay low for the duration
of the transaction. The SS pin on the master must be set high. If it goes
low, a mode fault error flag (MODF) is set in the SPSR.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS pin
could be set low as long as CPHA = 1 clock modes are used.
NOTE:
If the SPI is in master mode, this pin can be used as a general-purpose
output pin. If configured as an input pin while in master mode, it must be
set high.
MC68HC05V12 — Rev. 2.0
Serial Peripheral Interface (SPI)
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Technical Data