MC68HC05V12 Datasheet, PDF (89/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Core Timer
Core Timer Status and Control Register
8.3 Core Timer Status and Control Register
The core timer status and control register (CTSCR) contains:
• Timer interrupt flag
• Timer interrupt enable bits
• Real-time interrupt rate select bits
Figure 8-2 shows the value of each bit in the CTSCR when coming out
of reset.
Address: $0008
Bit 7
6
5
4
3
2
1
Bit 0
Read: CTOF RTIF
0
0
TOFE RTIE
RT1
RT0
Write
TOFC RTFC
Reset: 0
0
0
0
0
0
1
1
= Unimplemented
Figure 8-2. Core Timer Status and Control Register (CTSCR)
CTOF — Core Timer Overflow Bit
CTOF is a read-only status bit set when the 8-bit ripple counter rolls
over from $FF to $00. Clearing the CTOF is done by writing a 1 to
TOFC. Writing to this bit has no effect. Reset clears CTOF.
RTIF — Real Time Interrupt Flag
The real-time interrupt circuit consists of a 3-stage divider and a 1-of-
4 selector. The clock frequency that drives the RTI circuit is E/2**11
(or E/2048) with three additional divider stages giving a maximum
interrupt period of 7.8 milliseconds at a bus rate of 2.1 MHz. RTIF is
a clearable, read-only status bit and is set when the output of the
chosen (1-of-4 selection) stage goes active. Clearing the RTIF is
done by writing a 1 to RTFC. Writing has no effect on this bit. Reset
clears RTIF.
MC68HC05V12 — Rev. 2.0
Core Timer
For More Information On This Product,
Go to: www.freescale.com
Technical Data