MC68HC05V12 Datasheet, PDF (154/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital
Valid SOF Symbol
In Figure 14-10(4), if the active-to-passive received transition
beginning the next data bit (or symbol) occurs between c and d, the
current symbol would be considered a valid SOF symbol.
Valid BREAK Symbol
In Figure 14-11, if the next active-to-passive received transition does
not occur until after e, the current symbol will be considered a valid
BREAK symbol. A BREAK symbol should be followed by a start-of-
frame (SOF) symbol beginning the next message to be transmitted
onto the J1850 bus. See 14.5.2 J1850 Frame Format for BDLC
response to BREAK symbols.
240 µs
ACTIVE
PASSIVE
(2) VALID BREAK SYMBOL
e
Figure 14-11. J1850 VPW Received BREAK Symbol Times
14.5.5 Message Arbitration
Message arbitration on the J1850 bus is accomplished in a non-
destructive manner, allowing the message with the highest priority to be
transmitted, while any transmitters which lose arbitration simply stop
transmitting and wait for an idle bus to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that
another message is in progress, it waits until the bus is idle. However, if
multiple nodes begin to transmit in the same synchronization window,
message arbitration will occur beginning with the first bit after the SOF
symbol and continue with each bit thereafter. If a write to the BDR (for
instance, to initiate transmission) occurred on or before
104 • t_BDLC from the received rising edge, then the BDLC will transmit
Technical Data
Byte Data Link Controller – Digital (BDLC–D)
For More Information On This Product,
Go to: www.freescale.com
MC68HC05V12 — Rev. 2.0