MC68HC05V12 Datasheet, PDF (104/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
10.4.2 Serial Clock (SCK/PB1)
The master clock is used to synchronize data movement both in and out
of the device through its MOSI and MISO lines. The master and slave
devices are capable of exchanging a byte of information during a
sequence of eight clock cycles. Since SCK is generated by the master
device, this line becomes an input on a slave device.
As shown in Figure 10-1, four possible timing relationships may be
chosen by using control bits CPOL and CPHA in the serial peripheral
control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the
MOSI line a half cycle before the clock edge (SCK) for the slave device
to latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the
clock rate. In a slave device, SPR0 and SPR1 have no effect on the
operation of the SPI.
10.4.3 Master In/Slave Out (MISO/PB2)
The MISO line is configured as an input in a master device and as an
output in a slave device. It is one of the two lines that transfer serial data
in one direction, with the most significant bit sent first. The MISO line of
a slave device is placed in the high-impedance state if the slave is not
selected.
10.4.4 Master Out/Slave In (MOSI/PB3)
The MOSI line is configured as an output in a master device and as an
input in a slave device. It is one of the two lines that transfer serial data
in one direction with the most significant bit sent first.
Technical Data
Serial Peripheral Interface (SPI)
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MC68HC05V12 — Rev. 2.0