MC68HC05V12 Datasheet, PDF (169/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
BDLC CPU Interface
NBFS — Normalization Bit Format Select Bit
This bit controls the format of the normalization bit (NB). (See Figure
14-19.) SAE J1850 strongly encourages using an active long (logic 0)
for in-frame responses containing cyclical redundancy check (CRC)
and an active short (logic 1) for in-frame responses without CRC.
1 = NB that is received or transmitted is a 0 when the response part
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 1 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
0 = NB that is received or transmitted is a 1 when the response part
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 0 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
TEOD — Transmit End-of-Data Bit
This bit is set by the programmer to indicate the end of a message is
being sent by the BDLC. It will append an 8-bit CRC after completing
transmission of the current byte. This bit also is used to end an in-
frame response (IFR). If the transmit shadow register is full when
TEOD is set, the CRC byte will be transmitted after the current byte in
the Tx shift register and the byte in the Tx shadow register have been
transmitted. (See 14.6.3 Rx and Tx Shadow Registers for a
description of the transmit shadow register.) Once TEOD is set, the
transmit data register empty flag (TDRE) in the BDLC state vector
register (BSVR) is cleared to allow lower priority interrupts to occur.
See 14.7.4 BDLC State Vector Register.
1 = Transmit end-of-data (EOD) symbol
0 = The TEOD bit will be cleared automatically at the rising edge of
the first CRC bit that is sent or if an error is detected. When
TEOD is used to end an IFR transmission, TEOD is cleared
when the BDLC receives back a valid EOD symbol or an error
condition occurs.
MC68HC05V12 — Rev. 2.0
Byte Data Link Controller – Digital (BDLC–D)
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Technical Data