MC68HC05V12 Datasheet, PDF (59/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Interrupts
Reset Interrupt Sequence
4.4 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner as shown in Figure 4-1. A low-level input
on the RESET pin or internally generated RST signal causes the
program to vector to its starting address which is specified by the
contents of memory locations $3FFE and $3FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during this type of reset as described in Section 5. Resets.
4.5 Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt since
it is executed regardless of the state of the I bit in the CCR. If the I bit is
zero (interrupts enabled), the SWI instruction executes after interrupts
which were pending before the SWI was fetched or before interrupts
generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $3FFC and
$3FFD.
4.6 Hardware Interrupts
All hardware interrupts except reset are maskable by the I bit in the CCR.
If the I bit is set, all hardware interrupts (internal and external) are
disabled. Clearing the I bit enables the hardware interrupts. Two types
of hardware interrupts are explained in this section.
4.7 External Interrupt (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. A block
diagram of the IRQ function is shown in Figure 4-2.
NOTE:
The BIH and BIL instructions will apply only to the level on the IRQ pin
itself and not to the output of the logic OR function with the port C IRQ
interrupts. The state of the individual port C pins can be checked by
reading the appropriate port C pins as inputs.
MC68HC05V12 — Rev. 2.0
Interrupts
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