MC68HC05V12 Datasheet, PDF (198/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Gauge Drivers
Freescale Semiconductor, Inc.
6. Wait for sample and hold to settle.
7. Go back to step 1.
15.7.2 Scan Status and Control Register
Although the CDR and CMRs can be written at any time, the user may
want to write the CDR and CMRs at a particular time in the scanning
sequence. Some of the bits in the SSCR give the user the information
needed to synchronize the writes to the CDR and CMRs with the coil
sequencer.
In addition to the sychronization bits, this register also contains a bit that
affects the type of scanning that will take place (automatic or manual)
and a bit to initiate a scan cycle manually when using manual mode.
Address: $0021
BIt 7
6
5
4
3
2
1
Bit 0
Read:
SYNF
0
SYNIE
R
GCS1 GCS0 SCNS AUTOS
Write:
SYNR
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 15-13. Scan Status and Control Register (SSCR)
SYNIE — Synchronize Interrupt Enable Bit
When this bit is set, an interrupt signal will be sent to the CPU when
the SYNF bit is set. The I bit in the CPU condition code register must
be cleared in order for the interrupt to be recognized by the CPU. The
interrupt vector assigned to the gauge module is shown in
Table 15-2.
1 = Interrupt is enabled.
0 = Interrupt is disabled.
SYNF — Synchronize Flag Bit
This bit is a read-only status bit and indicates that the coil sequencer
has begun to service coil 11 (minor D). At this point in the scanning
cycle, it is safe to write any of the CMRs or CDRs without affecting the
Technical Data
Gauge Drivers
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MC68HC05V12 — Rev. 2.0