MC68HC05V12 Datasheet, PDF (92/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Core Timer
Freescale Semiconductor, Inc.
8.5 Core Timer Counter Register
The core timer counter register (CTCR) is a read-only register which
contains the current value of the 8-bit ripple counter at the beginning of
the timer chain. This counter is clocked by the CPU clock (E/4) and can
be used for various functions including a software input capture.
Extended time periods can be attained using the TOF function to
increment a temporary RAM storage location, thereby simulating a 16-
bit (or more) counter.
Address: $0009
Bit 7
6
5
4
3
2
1
Read: TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 8-3. Core Timer Counter Register (CTCR)
Bit 0
TMR0
0
The power-on cycle clears the entire counter chain and begins clocking
the counter. After 4064 cycles, the power-on reset circuit is released
which again clears the counter chain and allows the device to come out
of reset. At this point, if RESET is not asserted, the timer will start
counting up from 0 and normal device operation will begin. When
RESET is asserted any time during operation (other than POR), the
counter chain will be cleared.
8.6 Core Timer during Wait Mode
The CPU clock halts during wait mode, but the timer remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit
wait mode. The COP watchdog timer, derived from the core timer,
remains active in wait mode, if enabled via the mask option register
(MOR).
Technical Data
Core Timer
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MC68HC05V12 — Rev. 2.0