MC68HC05V12 Datasheet, PDF (166/246 Pages) Freescale Semiconductor, Inc – HCMOS Microcontreller Unit

Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital
defines the basic timing resolution of the MUX interface. They may be
written only once after reset, after which they become read-only bits.
The nominal frequency of f_BDLC must always be 1.048576 MHz or 1.0
MHz for J1850 bus communications to take place. Hence, the value
programmed into these bits is dependent on the chosen MCU system
clock frequency per Table 14-3.
Table 14-3. BDLC Rate Selection
f_XCLK Frequency
R1
1.049 MHz
0
2.097 MHz
0
4.194 MHz⁽¹⁾
1
8.389 MHz⁽¹⁾
1
1.000 MHz
0
2.000 MHz
0
4.000 MHz⁽¹⁾
1
8.000 MHz⁽¹⁾
1
1. Invalid option on this MCU.
R0
Division
0
1
1
2
0
4
1
8
0
1
1
2
0
4
1
8
f_BDLC
1.049 MHz
1.049 MHz
1.049 MHz
1.049 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
IE— Interrupt Enable Bit
This bit determines whether the BDLC will generate CPU interrupt
requests in run mode. It does not affect CPU interrupt requests when
exiting the BDLC stop or BDLC wait modes. Interrupt requests will be
maintained until all of the interrupt request sources are cleared by
performing the specified actions upon the BDLC’s registers. Interrupts
that were pending at the time that this bit is cleared may be lost.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
If the programmer does not wish to use the interrupt capability of the
BDLC, the BDLC state vector register (BSVR) can be polled
periodically by the programmer to determine BDLC states. See 14.7.4
BDLC State Vector Register for a description of the BSVR.
Technical Data
Byte Data Link Controller – Digital (BDLC–D)
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MC68HC05V12 — Rev. 2.0