Z51F0410 Datasheet, PDF (86/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
T0CR
T1CR
T0EN T0PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
1
X
0
X
X
X
X
X
ADDRESS
:
B2H
INITIAL VALUE : 0000_0000B
POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST
X
1
0
0
1
1
X
X
ADDRESS
:
B4H
INITIAL VALUE : 0000_0000B
EC0
fx
÷2
P
r
÷4
e ÷16
s
c
÷64
MUX
a ÷256
l
e
÷1024
r ÷4096
3
T0CK[2:0]
T0CN
T0ST
16-bit Counter
T0
(8Bit)
[B3H]
T1
(8Bit)
Clear
[B6H]
[B3H]
Comparator
T0DR
(8Bit)
T1DR
(8Bit) _[B5H]
16-bit Data Register
T0IF
F/F
Timer0
Interrupt
P04/T0
PIN
Figure 4.9 16 Bit Timer/Event Counter0, 1 Block Diagram
Note: Do not set T0DR to 0x00 in 16-bit mode. If T0DR is set to 0x00, Timer interrupt or count
match occur after T1DR+0x01. If you set T0DR to be 0x00, T1DR must have one fewer number of
count than the number of count which you want.
Example: If T1DR=0x01 and T0DR=0x00, counter match occurs when T1=0x02 and T0=0x00.
4.5.1.4 8-Bit Capture Mode
The timer 0, 1 capture mode is set by CAP0, CAP1 as ‘1’. The clock source can use the
internal/external clock. Basically, it has the same function of the 8-bit timer/counter mode and the
interrupt occurs at T0, T1 and T0DR, T1DR matching time, respectively. The capture result is loaded
into CDR0, CDR1. The T0, T1 value is automatically cleared by hardware and restarts counter.
This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider
than the maximum period of timer.
As the EIEDGE and EIPOLA register setting, the external interrupt INT0, INT1 function is chosen.
The CDR0, T0 and T0DR are in same address. In the capture mode, reading operation is read the
CDR0, not T0DR because path is opened to the CDR0. The CDR1 has the same function.
PS029502-0212
PRELIMINARY
83