Z51F0410 Datasheet, PDF (151/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
Figure 6.10 Internal Reset at the power fail situation
“H”
VDD
“H”
Internal nPOR
“H”
PAD RESETB (R20)
BOD_RESETB
BIT (for Config)
F1
00 01 02 ^{.. ..}
.. _{2F 30}
F1
BIT (for Reset)
Config Read
RESET_SYSB
INT-OSC (128KHz)
INT-OSC 128KHz/32
00
01 02 ^{.. ..}
250us X 30h = about 12ms
.. _{3F 40 00 01 02 03}
Main OSC Off
250us X 40h = about 16ms
INT-OSC 128KHz / 32 = 4KHz (250us)
Figure 6.11 Configuration timing when BOD RESET
6.7.1 Register Map
Name
BODR
Address
0x86
Table 6.3 BOD Register Map
Dir
Default
Description
R/W
81H
BOD Control Register
6.7.2 Reset Operation Register description
Reset control Register consists of the BOD Control Register (BODR).
6.7.3 Register description for Reset Operation
BODR (BOD Control Register) : 81H
7
PORF
R/W
6
EXTRF
R/W
5
WDTRF
R/W
4
OCDRF
R/W
3
BODRF
R/W
2
BODLS[1]
R/W
1
0
BODLS[0]
BODEN
R/W
R/W
Initial value : 81H
PORF
Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit.
0
No detection
PS029502-0212
PRELIMINARY
148