Z51F0410 Datasheet, PDF (127/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
STOP
START
0
I2C is in slave mode.
1
I2C is in master mode.
When I2C is master, generates STOP condition.
0
No operation
1
STOP condition is to be generated
When I2C is master, generates START condition.
0
No operation
1
START or repeated START condition is to be generated
I2CSR (I2C Status Register) : DBH
7
GCALL
R
6
TEND
R
5
STOP
R
4
SSEL
R
3
MLOST
R
2
BUSY
R
1
0
TMODE
RXACK
R
R
Initial value : 00H
GCALL
This bit has different meaning depending on whether I2C is master or
slave. Note 1)
When I2C is a master, this bit represents whether it received AACK
(Address ACK) from slave.
When I2C is a slave, this bit is used to indicate general call.
0
No AACK is received (Master mode)
1
AACK is received (Master mode)
0
Received address is not general call address (Slave mode)
TEND
1
General call address is detected (Slave mode)
This bit is set when 1-Byte of data is transferred completely. Note 1)
0
1 byte of data is not completely transferred
1
1 byte of data is completely transferred
STOP This bit is set when STOP condition is detected. Note 1)
0
No STOP condition is detected
1
STOP condition is detected
SSEL This bit is set when I2C is addressed by other master. Note 1)
0
I2C is not selected as slave
1
I2C is addressed by other master and acts as a slave
MLOST This bit represents the result of bus arbitration in master mode. Note 1)
0
I2C maintains bus mastership
1
I2C has lost bus mastership during arbitration process
BUSY This bit reflects bus status.
0
I2C bus is idle, so any master can issue a START condition
1
I2C bus is busy
TMODE
This bit is used to indicate whether I2C is transmitter or receiver.
0
I2C is a receiver
1
I2C is a transmitter
RXACK This bit shows the state of ACK signal.
0
No ACK is received
1
ACK is generated at ninth SCL period
Note 1) These bits can be source of interrupt.
When an I2C interrupt occurs except for STOP interrupt, the SCL line is hold LOW. To release SCL,
write arbitrary value to I2CSR. When I2CSR is written, the TEND, STOP, SSEL, LOST, RXACK bits
are cleared.
PS029502-0212
PRELIMINARY
124