Z51F0410 Datasheet, PDF (81/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
register, WTMR can control the clock source (WTCK), interrupt interval (WTIN) and function
enable/disable (WTEN). Also there is WT interrupt flag bit (WTIFR).
4.4.5 Register description for Watch Timer
WTMR (Watch Timer Mode Register) : 9DH
7
6
WTEN
-
R/W
-
5
4
3
2
1
0
-
WTIFR
WTIN1
WTIN0
WTCK1
WTCK0
-
R/W
R/W
R/W
R/W
R/W
Initial value :0 0H
WTEN Control Watch Timer
0
disable
1
enable
WTIFR
When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’
to this bit or auto clear by INT_ACK signal.
0
WT Interrupt no generation
1
WT Interrupt generation
WTIN[1:0] Determine interrupt interval
WTIN1 WTIN0 description
0
0
fwck/2^11
0
1
fwck/2^13
1
0
fwck/2^14
1
1
fwck/2^14 x (7bit WT Value)
WTCK[1:0] Determine Source Clock
WTCK1 WTCK0 description
0
0
fsub
0
1
fx/256
1
0
fx/128
1
1
fx/64
Remark: fx– Main system clock oscillation frequency
fsub- Sub clock oscillation frequency
fwck- selected Watch Timer clock
WTR (Watch Timer Register:Write Case) : 9EH
7
WTCL
W
6
WTR 6
W
5
WTR 5
W
4
WTR 4
W
3
WTR 3
W
2
WTR 2
W
1
WTR 1
W
0
WTR 0
W
Initial value : 7FH
WTCL Clear WT Counter
0
Free Run
1
Clear WT Counter (auto clear after 1 Cycle)
WTR[6:0] Set WT period
WT Interrupt Interval=(fwck/2^14) x(7bit WT Value+1)
Note) To guarantee proper operation, it is greater than 01H to write WTR.
WTCR (Watch Timer Counter Register:Read Case) : 9EH
7
6
5
4
3
2
1
0
WTCR 6
WTCR 5
WTCR 4
WTCR 3
WTCR 2
WTCR 1
WTCR 0
PS029502-0212
PRELIMINARY
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