Z51F0410 Datasheet, PDF (121/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
4.7.8.2 Master Receiver
To operate I2C in master receiver, follow the recommended steps below.
1. Enable I2C by setting IICEN bit in I2CMR. This provides main clock to the peripheral.
2. Load SLA+R into the I2CDR where SLA is address of slave device and R is transfer direction
from the viewpoint of the master. For master receiver, R is ‘1’. Note that I2CDR is used for
both address and data.
3. Configure baud rate by writing desired value to both I2CSCLLR and I2CSCLHR for the Low
and High period of SCL line.
4. Configure the I2CSDAHR to decide when SDA changes value from falling edge of SCL. If
SDA should change in the middle of SCL LOW period, load half the value of I2CSCLLR to the
I2CSDAHR.
5. Set the START bit in I2CMR. This transmits a START condition. And also configure how to
handle interrupt and ACK signal. When the START bit is set, 8-bit data in I2CDR is
transmitted out according to the baud-rate.
6. This is ACK signal processing stage for address packet transmitted by master. When 7-bit
address and 1-bit transfer direction is transmitted to target slave device, the master can know
whether the slave acknowledged or not in the 9^th high period of SCL. If the master gains bus
mastership, I2C generates GCALL interrupt regardless of the reception of ACK from the slave
device. When I2C loses bus mastership during arbitration process, the MLOST bit in I2CSR is
set, and I2C waits in idle state or can be operate as an addressed slave. To operate as a
slave when the MLSOT bit in I2CSR is set, the ACKEN bit in I2CMR must be set and the
received 7-bit address must equal to the SLA bits in I2CSAR. In this case I2C operates as a
slave transmitter or a slave receiver (go to appropriate section). In this stage, I2C holds the
SCL LOW. This is because to decide whether I2C continues serial transfer or stops
communication. The following steps continue assuming that I2C does not lose mastership
during first data transfer.
I2C (Master) can choose one of the following cases according to the reception of ACK signal
from slave.
1) Master receives ACK signal from slave, so continues data transfer because slave can
prepare and transmit more data to master. Configure ACKEN bit in I2CMR to decide whether
I2C ACKnowledges the next data to be received or not.
2) Master stops data transfer because it receives no ACK signal from slave. In this case, set
the STOP bit in I2CMR.
3) Master transmits repeated START condition due to no ACK signal from slave. In this case,
load SLA+R/W into the I2CDR and set START bit in I2CMR.
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of
3), move to step 6 after transmitting the data in I2CDR and if transfer direction bit is ‘0’ go to
master transmitter section.
7. 1-Byte of data is being received.
8. This is ACK signal processing stage for data packet transmitted by slave. I2C holds the SCL
LOW. When 1-Byte of data is received completely, I2C generates TEND interrupt.
I2C can choose one of the following cases according to the RXACK flag in I2CSR.
1) Master continues receiving data from slave. To do this, set ACKEN bit in I2CMR to
ACKnowledge the next data to be received.
2) Master wants to terminate data transfer when it receives next data by not generating ACK
signal. This can be done by clearing ACKEN bit in I2CMR.
3) Because no ACK signal is detected, master terminates data transfer. In this case, set the
STOP bit in I2CMR.
4) No ACK signal is detected, and master transmits repeated START condition. In this case,
PS029502-0212
PRELIMINARY
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