Z51F0410 Datasheet, PDF (66/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

3.8 Interrupt Enable Accept Timing
Z51F0410
Product Specification
System
Clock
Max. 4 Machine Cycle
Interrupt
goes
Active
Interrupt
Latched
4 Machine Cycle
Interrupt Processing
: LCALL & LJMP
Interrupt Routine
Figure 3.7 Interrupt Response Timing Diagram
3.9 Interrupt Service Routine Address
Basic Interval Timer
Vector Table Address
00B3H
01H
00B4H
25H
Basic Interval Timer
Service Routine Address
0125H
0EH
0126H
2EH
Figure 3.8 Correspondence between vector Table address and the entry address of ISP
3.10 Saving/Restore General-Purpose Registers
INTxx : PUSH
PSW
PUSH
DPL
PUSH
DPH
PUSH
B
PUSH ACC
··
Interrupt_Processing:
∙∙
POP
ACC
POP
B
POP
DPH
POP
DPL
POP
PSW
RETI
Main Task
Interrupt
Service Task
Saving
Register
Restoring
Register
Figure 3.9 Saving/Restore Process Diagram & Sample Source
PS029502-0212
PRELIMINARY
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