Z51F0410 Datasheet, PDF (54/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
2.3 I/O Port
2.3.1 I/O Ports
The Z51F0410 MCU features one I/O ports (P0). Each port can be easily configured by software as
I/O pin, internal pull up and open drain pin to meet various system configurations and design
requirements. Also P0 includes function that can generate interrupt according to change of state of
the pin.
2.3.2 Port Register
2.3.2.1 Data Register (P0)
Data Register is a bidirectional I/O port. If ports are configured as output ports, data can be written to
the corresponding bit of the P0. If ports are configured as input ports, the data can be read from the
corresponding bit of the P0.
2.3.2.2 Direction Register (P0IO)
Each I/O pin can independently used as an input or an output through the P0IO register. Bits cleared
in this read/write register will select the corresponding pin in P0 to become an input, setting a bit sets
the pin to output. All bits are cleared by a system reset.
2.3.2.3 Pull-up Resistor Selection Register (P0PU)
The on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up resistor selection
register (P0PU). The pull-up register selection controls the pull-up resister enable/disable of each port.
When the corresponding bit is 1, the pull-up resister of the pin is enabled. When 0, the pull-up resister
is disabled. All bits are cleared by a system reset.
2.3.2.4 Open-drain Selection Register (P0OD)
There is internally open-drain selection register (P0OD) in P0. The open-drain selection register
controls the open-drain enable/disable of each port. Ports become push-pull by a system reset. You
should connect an external resistor in open-drain output mode.
2.3.2.5 Debounce Enable Register (P0DB)
P0 support debounce function. Debounce time of each ports has 1us, but if P0[2] uses external reset
function, it has 3us debounce time. (except P0[2], other port initialization state is OFF)
2.3.2.6 Pin Change Interrupt Enable Register (P0PC)
The P0 can support Pin Change Interrupt function. Pin Change Interrupts PCI will trigger if any
PS029502-0212
PRELIMINARY
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