Z51F0410 Datasheet, PDF (77/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
4.3 WDT
4.3.1 Overview
The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or
the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting
malfunction can be selected either a reset CPU or an interrupt request. When the watchdog timer is
not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed
intervals. It is possible to use free running 8-bit timer mode (WDTRSON=’0’) or watch dog timer mode
(WDTRSON=’1’) as setting WDTMR[6] bit. If writing WDTMR[5] to ‘1’, WDT counter value is cleared
and counts up. After 1 machine cycle, this bit has ‘0’ automatically. The watchdog timer consists of 8-
bit binary counter and the watchdog timer data register. When the value of 8-bit binary counter is
equal to the 8 bits of WDTR, the interrupt request flag is generated. This can be used as Watchdog
timer interrupt or reset the CPU in accordance with the bit WDTRSON.
The clock source of Watch Dog Timer is BIT overflow output. The interval of watchdog timer interrupt
is decided by BIT overflow period and WDTR set value. The equation is as below
WDT Interrupt Interval = (BIT Interrupt Interval) X (WDTR Value+1)
4.3.2 Block Diagram
BIT Overflow
1/2, 1/4, 1/8
WDTEN
WCKDIV[1:0]
Watchdog Timer
Counter Register
WDTCR
[8EH]
Clear
To Reset
Circuit
Clear
WDTIFR
INT_ACK
Watchdog Timer
Register
[8EH]
WDTR
WDTCL
WDTRSON
WDTMR
WDTIF
4.3.3 Register Map
Name
WDTR
WDTCR
WDTMR
Address
8EH
8EH
8DH
Figure 4.3 WDT Block Diagram
Table 4.3 WDT Register Map
Dir
W
R
R/W
Default
FFH
00H
00H
Description
Watch Dog Timer Register
Watch Dog Timer Counter Register
Watch Dog Timer Mode Register
PS029502-0212
PRELIMINARY
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