Z51F0410 Datasheet, PDF (10/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
Figure 4.8 Operation Example of Timer/Event Counter0, 1 ................................................................ 82
Figure 4.9 16 Bit Timer/Event Counter0, 1 Block Diagram ................................................................. 83
Figure 4.10 8-bit Capture Mode for Timer0, 1..................................................................................... 84
Figure 4.11 Input Capture Mode Operation of Timer 0, 1 ................................................................... 85
Figure 4.12 Express Timer Overflow in Capture Mode ....................................................................... 85
Figure 4.13 16-bit Capture Mode of Timer 0, 1 ................................................................................... 86
Figure 4.14 PWM Mode...................................................................................................................... 87
Figure 4.15 Example of PWM at 4MHz .............................................................................................. 87
Figure 4.16 Example of Changing the Period in Absolute Duty Cycle at 4Mhz................................... 88
Figure 4.17 Timer4 16-bit Mode Block Diagram ................................................................................. 93
Figure 4.18 USART Block Diagram .................................................................................................... 97
Figure 4.19 Clock Generation Block Diagram..................................................................................... 98
Figure 4.20 Synchronous Mode XCKn Timing.................................................................................... 99
Figure 4.21 frame format .................................................................................................................. 100
Figure 4.22 Start Bit Sampling.......................................................................................................... 103
Figure 4.23 Sampling of Data and Parity Bit..................................................................................... 104
Figure 4.24 Stop Bit Sampling and Next Start Bit Sampling ............................................................. 104
Figure 4.25 SPI Clock Formats when UCPHA=0.............................................................................. 105
Figure 4.26 SPI Clock Formats when UCPHA=1.............................................................................. 106
Figure 4.27 I2C Block Diagram ........................................................................................................ 112
Figure 4.28 Bit Transfer on the I2C-Bus ........................................................................................... 113
Figure 4.29 START and STOP Condition ......................................................................................... 113
Figure 4.30 Data Transfer on the I2C-Bus........................................................................................ 114
Figure 4.31 Acknowledge on the I2C-Bus ........................................................................................ 114
Figure 4.32 Clock Synchronization during Arbitration Procedure...................................................... 115
Figure 4.33 Arbitration Procedure of Two Masters ........................................................................... 115
Figure 4.34 Formats and States in the Master Transmitter Mode ..................................................... 117
Figure 4.35 Formats and States in the Master Receiver Mode ......................................................... 119
Figure 4.36 Formats and States in the Slave Transmitter Mode ....................................................... 121
Figure 4.37 Formats and States in the Slave Receiver Mode........................................................... 123
Figure 4.38 ADC Block Diagram....................................................................................................... 127
Figure 4.39 A/D Analog Input Pin Connecting Capacitor .................................................................. 127
Figure 4.40 A/D Power(AVDD) Pin Connecting Capacitor................................................................ 127
Figure 4.41 ADC Operation for Align bit ........................................................................................... 128
Figure 4.42 A/D Converter Operation Flow....................................................................................... 128
Figure 4.43 Analog Comparator Block Diagram ............................................................................... 132
Figure 5.1 IDLE Mode Release Timing by External Interrupt ............................................................ 138
Figure 5.2 STOP Mode Release Timing by External Interrupt .......................................................... 139
Figure 5.3 STOP1, 2 Mode Release Flow ........................................................................................ 140
Figure 6.1 RESET Block Diagram .................................................................................................... 142
Figure 6.2 Reset noise canceller time diagram................................................................................. 143
Figure 6.3 Fast VDD rising time........................................................................................................ 143
Figure 6.4 Internal RESET Release Timing On Power-Up ............................................................... 143
Figure 6.5 Configuration timing when Power-on ............................................................................... 144
Figure 6.6 Boot Process Wave Form................................................................................................ 145
Figure 6.7 Timing Diagram after RESET .......................................................................................... 146
Figure 6.8 Oscillator generating waveform example......................................................................... 146
Figure 6.9 Block Diagram of BOD .................................................................................................... 147
PS029502-0212
PRELIMINARY
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