Z51F0410 Datasheet, PDF (30/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

1.11.3 P0[2] Port Structure
Output
Input
Pull-up Enable
Open-Drain
Output Data
0
ACK_OUT ¹
ACK_OUT_EN
Direction
P0DA_OEB
P0RDA_OEB
Data
PAD DATA
RESETB_EN
(from Config)
1
0
Secondary
Input
Analog
Input
PCI_EN[2]
PCI_IN[2]
ACK_IN_EN
ACK_IN
RESETB_EN
RESETB
AN2
AN2_EN
Z51F0410
Product Specification
VDD
VDD
RESETB / AN2 /
ACK / P0[2]
LPF
Figure 1.20 RESETB / AN2 / ACK / P0[2] Port Structure
If the RESETB_EN (from config data) is 1, the input secondary data path is enabled with the highest
priority level and it automatically enables the pull-up function regardless of pull-up register value.
The analog channel selection bit enables the path of the AN2 and disable normal logic data path to
prevent the input gate leakage current. When the direction register value is 0, the input data is always
external PAD voltage.
The pull-up resister is directly controlled by the pull-up register bit regardless of current port direction.
The open-drain control is also by open-drain register. On open-drain mode, the push-pull drives just
N-MOS. When the direction is output (value 1), the output PAD voltage is controlled by push-pull
driver for the current output data. The secondary input or analog channel selection bit disable the
output direction regardless of the current direction register. The secondary input ACK_IN_EN,
PCI_EN[2] enable the input data path continuously. On normal read mode (non secondary mode), the
input data path is only enabled during the CPU OEB (active low). When the analog channel (AN2) is
enabled, the first input gate from the PAD except of RESET enabled is disabled (highest priority) to
prevent the input leakage current for the floating voltage status. At read operation, the input data is
selected by PAD direction register. If its value is ‘1’, it reads the current output register value.
PS029502-0212
PRELIMINARY
27