Z51F0410 Datasheet, PDF (129/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
SLA7
R/W
SLA6
R/W
SLA5
R/W
SLA[7:1]
GCALLEN
SLA4
R/W
SLA3
R/W
SLA2
R/W
SLA1
R/W
GCALLEN
R/W
Initial value : 00H
These bits configure the slave address of this I2C module when I2C
operates in slave mode.
This bit decides whether I2C allows general call address or not
when I2C operates in slave mode.
0
Ignore general call address
1
Allow general call address
4.8 12-Bit A/D Converter
4.8.1 Overview
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding
12-bit digital value. The A/D module has tenth analog inputs. The output of the multiplex is the input
into the converter, which generates the result via successive approximation. The A/D module has four
registers which are the control register ADCM (A/D Converter Mode Register), ADCM2 (A/D
Converter Mode Register 2) and A/D result register ADCHR (A/D Converter Result High Register) and
ADCLR (A/D Converter Result Low Register). It is selected for the corresponding channel to be
converted by setting ADSEL[3:0]. To executing A/D conversion, ADST bit sets to ‘1’. The register
ADCHR and ADCLR contains the results of the A/D conversion. When the conversion is completed,
the result is loaded into the ADCHR and ADCLR, the A/D conversion status bit AFLAG is set to ‘1’,
and the A/D interrupt is set. For processing A/D conversion, AFLAG bit is read as ‘0’. If using STBY
(power down) bit, the ADC is disabled. Also internal timer, external generating event, comparator, the
trigger of timer1pwm and etc. can start ADC regardless of interrupt occurrence.
ADC Conversion Time = ADCLK * 60 cycles
After STBY bit is reset (ADC power enable) and it is restarted, during some cycle, ADC conversion
value may have an inaccurate value.
PS029502-0212
PRELIMINARY
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