Z51F0410 Datasheet, PDF (32/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

1.11.4 P0[3] Port Structure
Output
Input
Pull-up Enable
OCD_EN
Open-Drain
Output Data
0
0
SS_OUT 1
1
SS_OUT_EN
ACO_OUT
ACO_OUT_EN
Direction
P0DA_OEB
P0RDA_OEB
Data
PAD DATA
Secondary
Input
Analog
Input
PCI_EN[3]
PCI_IN[3]
SS_IN_EN
SS
INT0_EN
INT0
EC0_EN
EC0
AN3
AN3_EN
1
0
NC20NS
NC20NS
Z51F0410
Product Specification
VDD
VDD
P03 / INT0 / SS /
EC0 / AN3 /
ACOUT / (DSCL)
LPF
Figure 1.21 P0[3] / INT0 / SS / EC0 / AN3 / ACOUT Port Structure
The pull-up resister is directly controlled by the pull-up register bit regardless of current port direction.
The open-drain control is also by open-drain register. On open-drain mode, the push-pull drives just
N-MOS. The OCD mode enable the Open-drain Output regardless of the Open-Drain Register value.
When the direction is output (value 1), the output PAD voltage is controlled by push-pull driver for the
current output data. The secondary input or analog channel selection bit disable the output direction
regardless of the current direction register. The secondary input SS_EN, INT0_EN, EC0_EN,
PCI_EN[3] enable the input data path continuously. On normal read mode (non secondary mode), the
input data path is only enabled during the CPU OEB (active low). When the analog channel (AN3) is
enabled, the first input gate from the PAD is disabled (highest priority) to prevent the input leakage
current for the floating voltage status. At read operation, the input data is selected by PAD direction
PS029502-0212
PRELIMINARY
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