Z51F0410 Datasheet, PDF (64/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

3.6 Effective Timing after Controlling Interrupt bit
Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3)
Z51F0410
Product Specification
Interrupt Enable Register
command
Next Instruction
Next Instruction
After executing IE set/clear, enable
register is effective.
Figure 3.4 Effective Timing of Interrupt Enable Register
Case b) Interrupt flag Register
Interrupt Flag Register
Command
Next Instruction
Next Instruction
After executing next instruction,
interrupt flag result is effective.
Figure 3.5 Effective Timing of Interrupt Flag Register
3.7 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority
level is serviced. If requests of the interrupt are received at the same time simultaneously, an interrupt
polling sequence determines by hardware which request is serviced. However, multiple processing
through software for special features is possible.
PS029502-0212
PRELIMINARY
61