Z51F0410 Datasheet, PDF (148/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
Reset Release
Config Read
②
POR
:VDD Input
:Internal OSC
⑥
④
①
③
⑤
⑦
Figure 6.6 Boot Process Wave Form
Table 6.2 Boot Process Description
Process
Description
Remarks
①
-No Operation
-1st POR level Detection
②
-Internal OSC (128KHz) ON
-about 1.4V ~ 1.5V
- (INT-OSC128KHz/32) 30h Delay section (=12ms)
③
-VDD input voltage must rise over than flash ^{-Slew Rate 0.025V/ms}
operating voltage for Config read
④
- Config read point
-about 1.5V ~ 1.6V
-Config Value is determined by
Writing Option
⑤
- Rising section to Reset Release Level
-16ms point after POR or
Ext_reset release
- Reset Release section (BIT overflow)
⑥
i) after16ms, after External Reset Release (External - BIT is used for Peripheral
reset)
stability
ii) 16ms point after POR (POR only)
⑦
-Normal operation
6.6 External RESETB Input
The External RESETB is the input to a Schmitt trigger. A reset in accomplished by holding the reset
pin low for at least 7us over, within the operating voltage range and oscillation stable, it is applied, and
the internal state is initialized. After reset state becomes ‘1’, it needs the stabilization time with 16ms
PS029502-0212
PRELIMINARY
145