Z51F0410 Datasheet, PDF (154/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
7.2 Two-pin external interface
7.2.1 Basic transmission packet
 10-bit packet transmission using two-pin interface.
 1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge.
 Parity is even of ‘1’ for 8-bit data in transmitter.
 Receiver generates acknowledge bit as ‘0’ when transmission for 8-bit data and its parity has no
error.
 When transmitter has no acknowledge (Acknowledge bit is ‘1’ at tenth clock), error process is
executed in transmitter.
 When acknowledge error is generated, host PC makes stop condition and transmits command
which has error again.
 Background debugger command is composed of a bundle of packet.
 Star condition and stop condition notify the start and the stop of background debugger command
respectively.
Figure 7.2 10-bit transmission packet
PS029501-0212
PRELIMINARY
151