Z51F0410 Datasheet, PDF (73/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
4.1.3 Register Map
Name
SCCR
Address
8AH
Table 4.1 SSCR Register Map
Dir
Default
Description
R/W
04H
System and Clock Control Register
4.1.4 Clock Generator Register description
The Clock Generation Register uses clock control for system operation. The clock generation
consists of System and Clock register.
4.1.5 Register description for Clock Generator
SCCR (System and Clock Control Register) : 8AH
7
6
WONS
DIV1
R/W
R/W
5
4
3
2
1
0
DIV0
CBYS
ISTOP
XSTOP
CS1
CS0
R/W-
R/W
R/W
R/W
R/W
R/W
Initial value : 04H
WONS
DIV[1:0]
CBYS
ISTOP
XSTOP
CS[1:0]
Control the operation of WDT RC-Oscillation during stop mode
0
WDTRC-Oscillator is disabled at stop mode (=STOP2)
1
WDTRC-Oscillator is enabled at stop mode (=STOP1)
When using fINTRC as system clock, determine division rate.
Note) when using fINTRC as system clock, only division rate come
into effect.
Note) To change by software, CBYS set to ‘1’
DIV1 DIV0 description
0
0
fINTRC/1 (8MHz)
0
1
fINTRC/2 (4MHz)
1
0
fINTRC/4 (2MHz)
1
1
fINTRC/8 (1MHz)
Control the scheme of clock change. If this bit set to ‘0’, clock
change is controlled by hardware. But if this set to ‘1’, clock change
is controlled by software. Ex) when setting CS[1:0], if CBYS bit set
to ‘0’, it is not changed right now, CPU goes to STOP mode and
then when wake-up, it applies to clock change.
Note) when clear this bit, keep other bits in SCCR
0
Clock changed by hardware during stop mode (default)
1
Clock changed by software. After clock is changed, it
should be cleared for low power.
Control the operation of INT-RC Oscillation
Note) when CBYS=’1’, It is applied
0
RC-Oscillation enable (default)
1
RC-Oscillation disable
Control the operation of X-Tal Oscillation
Note1) when CBYS=’1’, It is applied
Note2) if XINENA bit in FUSE_CONF to ‘0’, XSTOP is fixed to ‘1’
0
X-Tal Oscillation enable
1
X-Tal Oscillation disable (default)
Determine System Clock
Note) by CBYS bit, reflection point is decided
CS1 CS0 description
PS029502-0212
PRELIMINARY
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