Z51F0410 Datasheet, PDF (108/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
UCPHA and UCPOL bits in UCTRL1 register have different meanings according to the UMSEL[1:0]
bits which decides the operating mode of USART.
Table below shows four combinations of UCPOL and UCPHA for SPI mode 0, 1, 2, and 3.
Table 4.10 CPOL Functionality
SPI Mode
0
1
2
3
UCPOL
0
0
1
1
UCPHA
0
1
0
1
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
XCK
(UCPOL=0)
XCK
(UCPOL=1)
SAMPLE
MOSI
MSB First
LSB First
MISO
BIT7
BIT0
BIT6
BIT1
…
BIT2
BIT1
BIT0
…
BIT5
BIT6
BIT7
/SS OUT
(MASTER)
/SS IN
(SLAVE)
When UCPHA=0, the slave^Fb^ige^ug^rin^es⁴t^.2o⁵d^Sri^Pv^Ie^Cit^ls^ocM^kI^FS^oO^rmo^au^tt^spu^wt^hw^eiⁿth^Ut^Ch^Pe^Hfi^Ars⁼t⁰data bit value when SS goes
to active low. The first XCK edge causes both the master and the slave to sample the data bit value
on their MISO and MOSI inputs, respectively. At the second XCK edge, the USART shifts the second
data bit value out to the MOSI and MISO outputs of the master and slave, respectively. Unlike the
case of UCPHA=1, when UCPHA=0, the slave’s SS input must go to its inactive high level between
transfers. This is because the slave can prepare the first data bit when it detects falling edge of SS
input.
PS029502-0212
PRELIMINARY
105