Z51F0410 Datasheet, PDF (67/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
3.11 Interrupt Timing
SCLK
CLP2
INT_SRC
INTR_ACK
LAST_CYC
INTR_LCALL
INT_VEC
PROGA
Interrupt sampled here
CLP1
CLP2
C1P1
C1P2
C2P1
C2P2
8-Bit interrupt Vector
{8’h00, INT_VEC}
Figure 3.10 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Interrupt source sampled at last cycle of the command. When sampling interrupt source, it is decided
to low 8-bit of interrupt vector. M8051W core makes interrupt acknowledge at first cycle of command,
executes long call to jump interrupt routine as INT_VEC.
Note) command cycle C?P?: L=Last cycle, 1=1^st cycle or 1^st phase, 2=2^nd cycle or 2^nd phase
3.12 Interrupt Register Overview
3.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3)
Interrupt enable register consists of Global interrupt control bit (EA) and peripheral interrupt control
bits. Totally 24 peripheral are able to control interrupt.
3.12.2 Interrupt Priority Register (IP, IP1)
The 24 interrupt divides 6 groups which have each 4 interrupt sources. A group can decide 4 levels
interrupt priority using interrupt priority register. Level 3 is the high priority, while level 0 is the low
priority. Initially, IP, IP1 reset value is ‘0’. At that initialization, low interrupt number has a higher
priority than high interrupt number. If decided the priority, low interrupt number has a higher priority
than high interrupt number in that group.
PS029502-0212
PRELIMINARY
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