Z51F0410 Datasheet, PDF (125/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
address equals to SLA bits, when the ACKEN bit is disabled, I2C enters idle state. When
SSEL interrupt occurs and I2C is ready to receive data, write arbitrary value to I2CSR to
release SCL line.
5. 1-Byte of data is being received.
6. In this step, I2C generates TEND interrupt and holds the SCL line LOW regardless of the
reception of ACK signal from master. Slave can select one of the following cases.
1) No ACK signal is detected (ACKEN=0) and I2C waits STOP or repeated START condition.
2) ACK signal is detected (ACKEN=1) and I2C can continue to receive data from master.
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1) move to step 7 to terminate communication. In case of 2) move to step 5. In either
case, a repeated START condition can be detected. For that case, move step 4.
7. This is the final step for slave receiver function of I2C, handling STOP interrupt. The STOP bit
indicates that data transfer between master and slave is over. To clear I2CSR, write arbitrary
value to I2CSR. After this, I2C enters idle state.
The process can be depicted as following figure when I2C operates in slave receiver mode.
LOST&
IDLE
S or Sr
SLA+W
0x95
0x1D
ACK ^N
Y
0x15
GCALL
DATA
Y
0x45
ACK
Y
N
0x44
0x20
STOP
P
IDLE
From master to slave /
Master command or Data Write
From slave to master
0xxx _{Value of Status Register}
ACK ^{Interrupt, SCL line is held low}
P Interrupt after stop command
LOST&
Arbitration lost as master and
addressed as slave
GCALL General Call Address
PS029502-0212
PRELIMINARY
122