Z51F0410 Datasheet, PDF (28/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

1.11 Port Structure Diagram (detail view)
1.11.1 P0[0] Port Structure
Output
Input
Pull-up Enable
Open-Drain
Output data
0
TXD_OUT
1
RXD_OUT_EN
Direction
P0DA_OEB
P0RDA_OEB
Data
PAD DATA
Secondary
Input
RXD_IN_EN
RXD
PCI_EN[0]
PCI_IN[0]
Analog
Input
AN0
AN0_EN (from PSR)
XIN_EN (from Config)
XIN(SUBXIN)
1
0
NC20NS
Z51F0410
Product Specification
VDD
VDD
XIN(SUBXIN) /
AN0 / RXD(TXD) /
P00
LPF
Figure 1.18 XIN(SUBXIN) / AN0 /RXD /P0[0] Port Structure
The pull-up resister is directly controlled by the pull-up register bit regardless of current port direction.
The open-drain control is also by open-drain register. On open-drain mode, the push-pull drives just
N-MOS. When the direction is output (value 1), the output PAD voltage is controlled by push-pull
driver for the current output data. The secondary input or analog channel selection bit disable the
output direction regardless of the current direction register. The secondary input RXD_EN, PCI_EN[0]
enables the input data path continuously. On normal read mode (non secondary mode), the input data
path is only enabled during the CPU OEB (active low). When the analog channel (AN0) is enabled,
the first input gate from the PAD is disabled (highest priority) to prevent the input leakage current for
the floating voltage status. The XIN function disables all analog channels and secondary input/output.
At read operation, the input data is selected by PAD direction register. If its value is ‘1’, it reads the
current output register value. Otherwise, it reads the current PAD voltage directly (just during OEB
active). In addition, always the current PAD voltage is read by PAD DATA register.
PS029502-0212
PRELIMINARY
25