Z51F0410 Datasheet, PDF (122/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
load SLA+R/W into the I2CDR and set the START bit in I2CMR.
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1) and 2), move to step 7. In case of 3), move to step 9 to handle STOP interrupt. In
case of 4), move to step 6 after transmitting the data in I2CDR, and if transfer direction bit is
‘0’ go to master transmitter section.
9. This is the final step for master receiver function of I2C, handling STOP interrupt. The STOP
bit indicates that data transfer between master and slave is over. To clear I2CSR, write
arbitrary value to I2CSR. After this, I2C enters idle state.
The processes described above for master receiver operation of I2C can be depicted as the following
figure.
Master
Transmitter
SLA+W
S or Sr
SLA+R
N
ACK
0x85 ^Y
0x84
0x20
STOP
P
0x0C
LOST
DATA
Rs
0x44
N
ACK
0x45 _Y
0x44
0x0C
LOST LOST&
0x0D 0x1D 0x1F ^{Slave Receiver (0x1D)}
or Transmitter (0x1F)
Sr
0x20
STOP
P
LOST ^{Other master continues}
0xxx
From master to slave /
Master command or Data Write
From slave to master
Value of Status Register
ACK
ACK
Interrupt, SCL line is held low
P
Interrupt after stop command
LOST&
Arbitration lost as master and
addressed as slave
Figure 4.35 Formats and States in the Master Receiver Mode
4.7.8.3 Slave Transmitter
To operate I2C in slave transmitter, follow the recommended steps below.
PS029502-0212
PRELIMINARY
119