Z51F0410 Datasheet, PDF (142/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
5.4 STOP mode
The power control register is set to ‘03h’ to enter the STOP Mode. In the stop mode, the main
oscillator, system clock and peripheral clock is stopped, but watch timer continue to operate. With the
clock frozen, all functions are stopped, but the on-chip RAM and control registers are held.
The source for exit from STOP mode is hardware reset and interrupts. The reset re-defines all the
control registers.
When exit from STOP mode, enough oscillation stabilization time is required to normal operation.
Figure 5.2 shows the timing diagram. When released from STOP mode, the Basic interval timer is
activated on wake-up. Therefore, before STOP instruction, user must be set its relevant prescale
divide ratio to have long enough time. this guarantees that oscillator has started and stabilized.
OSC
CPU Clock
External
Interrupt
BIT Counter
STOP Instruction
Execute
n
n+1 N+2 n+3
Normal Operation
STOP Operation
Release
0
1
FE FF
0
1
Clear & Start
By Software setting
Normal Operation
Before executed STOP instruction, BIT must be set properly by
software to get stabilization.
Figure 5.2 STOP Mode Release Timing by External Interrupt
PS029502-0212
PRELIMINARY
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