Z51F0410 Datasheet, PDF (110/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
4.6.12 USART Register description
USART module consists of USART Control 1 Register (UCTRL1), USART Control 2 Register
(UCTRL2), USART Control 3 Register (UCTRL3), USART Status Register (USTAT), USART Data
Register (UDATA), and USART Baud Rate Generation Register (UBAUD).
4.6.13 Register description for USART
UCTRL1 (USART Control 1 Register) : E2H
7
UMSEL1
R/W
6
UMSEL0
R/W
5
UPM1
R/W
4
UPM0
R/W
3
USIZE2
R/W
2
USIZE1
UDORD
R/W
1
0
USIZE0
UCPHA
UCPOL
R/W
R/W
Initial value : 00H
UMSEL[1:0] Selects operation mode of USART.
UMSEL1 UMSEL0 Operation Mode
0
0
Asynchronous Mode (Uart)
0
1
Synchronous Mode
1
0
Reserved
1
1
SPI Mode
UPM[1:0] Selects Parity Generation and Check methods
UPM1 UPM0 Parity
0
0
No Parity
0
1
Reserved
1
0
Even Parity
1
1
Odd Parity
USIZE[2:0] When in asynchronous or synchronous mode of operation, selects the
length of data bits in frame.
USIZE2 USIZE1 USIZE0 Data Length
0
0
0
5 bit
0
0
1
6 bit
0
1
0
7 bit
0
1
1
8 bit
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
9 bit
UDORD
This bit is in the same bit position with USIZE1. In SPI mode, when set to
one the MSB of the data byte is transmitted first. When set to zero the
LSB of the data byte is transmitted first.
0
LSB First
1
MSB First
UCPOL Selects polarity of XCK in synchronous or spi mode
0
TXD change @Rising Edge, RXD change @Falling Edge
1
TXD change @ Falling Edge, RXD change @ Rising Edge
UCPHA
This bit is in the same bit position with USIZE0. In SPI mode, along
with UCPOL bit, selects one of two clock formats for different kinds
of synchronous serial peripherals. Leading edge means first XCK
edge and trailing edge means 2^nd or last clock edge of XCK in one
XCK pulse. And Sample means detecting of incoming receive bit,
Setup means preparing transmit data.
PS029502-0212
PRELIMINARY
107