Z51F0410 Datasheet, PDF (36/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

1.11.6 P0[5] Port Structure
Output
Input
Pull-up Enable
OCD_EN
I2C_EN
PIN_MODE0
Open-Drain
Output Data
0
SDA_OUT ¹
0
PWM1O
0
1
BUZO
1
I2C_EN
PWM1O_EN
BUZO_EN
Direction
P0DA_OEB
P0RDA_OEB
Data
1
0
PAD DATA
Secondary
Input
I2C_EN
SDA_IN
PCI_EN[5]
PCI_IN[5]
Analog
Input
AN5
AN5_EN
AC+
AC+ EN
Z51F0410
Product Specification
VDD
VDD
P0[5]/SDA/PWM1
O/BUZ/AN5/AC+
LPF
Figure 1.23 P0[5]/SDA/PWM1O/BUZ/AN5/AC+ Port Structure
The pull-up resister is directly controlled by the pull-up register bit regardless of current port direction.
The open-drain control is also by open-drain register. On open-drain mode, the push-pull drive just N-
MOS. The I2C Mode and OCD Mode enable the Open-drain Output regardless of the Open-Drain
Register value. When the direction is output (value 1), the output PAD voltage is controlled by push-
pull driver for the current output data. The secondary input or analog channel selection bit disable the
output direction regardless of the current direction register. The secondary input SDA_IN_EN,
PCI_EN[5] enables the input data path continuously. On normal read mode (non secondary mode),
the input data path is only enabled during the CPU OEB (active low). When the analog channel (AN5)
is enabled, the first input gate from the PAD is disabled (highest priority) to prevent the input leakage
current for the floating voltage status. The AC+ function disables all analog channels and secondary
input/output. At read operation, the input data is selected by PAD direction register. If its value is ‘1’, it
PS029502-0212
PRELIMINARY
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