Z51F0410 Datasheet, PDF (113/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
DOR
FE
PE
bit initializes the internal logic of USART and is auto cleared.
0
No operation
1
Reset USART
This bit is set if a Data OverRun occurs. While this bit is set, the incoming
data frame is ignored. This flag is valid until the receive buffer is read.
0
No Data OverRun
1
Data OverRun detected
This bit is set if the first stop bit of next character in the receive buffer is
detected as ‘0’. This bit is valid until the receive buffer is read.
0
No Frame Error
1
Frame Error detected
This bit is set if the next character in the receive buffer has a Parity Error
when received while Parity Checking is enabled. This bit is valid until the
receive buffer is read.
0
No Parity Error
1
Parity Error detected
UBAUD (USART Baud-Rate Generation Register) : E6H
7
UBAUD7
R/W
6
UBAUD 6
R/W
5
UBAUD 5
R/W
4
UBAUD 4
R/W
3
UBAUD 3
R/W
2
UBAUD 2
R/W
1
0
UBAUD 1 UBAUD 0
R/W
R/W
Initial value : FFH
UBAUD [7:0]
The value in this register is used to generate internal baud rate in
asynchronous mode or to generate XCK clock in synchronous or spi
mode. To prevent malfunction, do not write ‘0’ in asynchronous
mode, and do not write ‘0’ or ‘1’ in synchronous or spi mode.
UDATA (USART Data Register) : E7H
7
UDATA7
R/W
6
UDATA6
R/W
5
UDATA 5
R/W
4
UDATA 4
R/W
3
UDATA 3
R/W
2
UDATA 2
R/W
1
0
UDATA 1 UDATA 0
R/W
R/W
Initial value : FFH
UDATA [7:0]
The USART Transmit Buffer and Receive Buffer share the same I/O
address with this DATA register. The Transmit Data Buffer is the
destination for data written to the UDATA register. Reading the
UDATA register returns the contents of the Receive Buffer.
Write this register only when the UDRE flag is set. In spi or
synchronous master mode, write this register even if TX is not
enabled to generate clock, XCK.
4.6.14 Baud Rate setting (example)
Table 4.12 Examples of UBAUD Settings for Commonly Used Oscillator Frequencies
Baud
Rate
2400
4800
9600
14.4K
fOSC=1.00MHz
U2X=0
U2X=1
UBAUD ERROR UBAUD ERROR
25
0.2%
51
0.2%
12
0.2%
25
0.2%
6
-7.0%
12
0.2%
3
8.5%
8
-3.5%
fOSC=1.8432MHz
U2X=0
U2X=1
UBAUD ERROR UBAUD ERROR
47
0.0%
95
0.0%
23
0.0%
47
0.0%
11
0.0%
23
0.0%
7
0.0%
15
0.0%
fOSC=2.00MHz
U2X=0
U2X=1
UBAUD ERROR UBAUD ERROR
51
0.2%
103
0.2%
25
0.2%
51
0.2%
12
0.2%
25
0.2%
8
-3.5%
16
2.1%
PS029502-0212
PRELIMINARY
110