Z51F0410 Datasheet, PDF (103/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
A frame starts with the start bit followed by the least significant data bit (LSB). Then the next data
bits, up to a total of nine, are succeeding, ending with the most significant bit (MSB). If enabled the
parity bit is inserted after the data bits, before the stop bits. A high to low transition on data pin is
considered as start bit. When a complete frame is transmitted, it can be directly followed by a new
frame, or the communication line can be set to an idle state. The idle means high state of data pin.
The next figure shows the possible combinations of the frame formats. Bits inside brackets are
optional.
1 data frame
Idle St
D0
D1
D2
D3
D4 [D5] [D6] [D7] [D8] [P] Sp1 [Sp2 Idle / St
]
Character
bits
Figure 4.21 frame format
1 data frame consists of the following bits
• Idle No communication on communication line (TxD/RxD)
• St
Start bit (Low)
• Dn
Data bits (0~8)
• Parity bit ------------ Even parity, Odd parity, No parity
• Stop bit(s) ---------- 1 bit or 2 bits
The frame format used by the USART is set by the USIZE[2:0], UPM[1:0] and USBS bits in UCTRL1
register. The Transmitter and Receiver use the same setting.
4.6.7 Priority bit
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result
of the exclusive-or is inverted. The parity bit is located between the MSB and first stop bit of a serial
frame.
P_even = D_n-1 ^ … ^ D₃ ^ D₂ ^ D₁ ^ D₀ ^ 0
P_odd = D_n-1 ^ … ^ D₃ ^ D₂ ^ D₁ ^ D₀ ^ 1
P_even : Parity bit using even parity
P_odd : Parity bit using odd parity
D_n : Data bit n of the character
4.6.8 USART Transmitter
The USART Transmitter is enabled by setting the TXE bit in UCTRL1 register. When the Transmitter
is enabled, the normal port operation of the TXD pin is overridden by the serial output pin of USART.
The baud-rate, operation mode and frame format must be setup once before doing any transmissions.
If synchronous or spi operation is used, the clock on the XCK pin will be overridden and used as
transmission clock. If USART operates in spi mode, SS pin is used as SS input pin in slave mode or
can be configured as SS output pin in master mode. This can be done by setting SPISS bit in
UCTRL3 register.
PS029502-0212
PRELIMINARY
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