Z51F0410 Datasheet, PDF (76/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
4.2.4 Bit Interval Timer Register description
The Bit Interval Timer Register consists of BIT Clock control register (BCCR) and Basic Interval
Timer register (BITR). If BCLR bit set to ‘1’, BITR becomes ‘0’ and then counts up. After 1 machine
cycle, BCLR bit is cleared as ‘0’ automatically.
4.2.5 Register description for Bit Interval Timer
BCCR (BIT Clock Control Register) : 8BH
7
6
5
4
3
2
1
0
BITF
-
-
-
BCLR
BCK2
BCK1
BCK0
R/W
R
R
R
R/W
R/W
R/W
R/W
Initial value : 05H
BITF
BCLR
BCK[2:0]
When BIT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’
to this bit.
0
no generation
1
generation
If BCLK Bit is written to ‘1’, BIT Counter is cleared as ‘0’
0
Free Running
1
Clear Counter
Select BIT overflow period (BIT Clock=4 KHz)
BCK2 BCK1 BCK0
0
0
0
0.5msec (BIT Clock * 2)
0
0
1
1msec
0
1
0
2msec
0
1
1
4msec
1
0
0
8msec
1
0
1
16msec (default)
1
1
0
32msec
1
1
1
64msec
BITR (Basic Interval Timer Register) : 8CH
7
6
5
4
3
2
1
0
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
R
R
R
R
R
R
R
R
Initial value : 00H
BIT[7:0] BIT Counter
PS029502-0212
PRELIMINARY
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