Z51F0410 Datasheet, PDF (115/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
4.7 I2C
4.7.1 Overview
The I2C is one of industrial standard serial communication protocols, and which uses 2 bus lines
Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL
lines are open-drain output, each line needs pull-up resistor. The features are as shown below.
- Compatible with I2C bus standard
- Multi-master operation
- Up to 400 KHz data transfer speed
- 7 bit address
- Both master and slave operation
- Bus busy detection
4.7.2 Block Diagram
SDA
SCL
Debounce
enable
Slave Address Register
(SVADR)
Noise
Canceller
(debounce)
1 ^SDAIN
F/F
0
I
8-bit Shift Register
n
(SHFTR)
t
e
r
n
SDAOUT
SDA
Data Out Register
a
Out Controller
(I2CDR)
l
B
u
Debounce
enable
SCLIN
s
SCL High Period Register
(I2CSCLHR)
L
Noise
Canceller
1
(debounce)
SCL
Out Controller
SCL Low Period Register
(I2CSCLLR)
i
n
e
0
SDA Hold Time Register
(I2CDAHR)
SCLOUT
Figure 4.27 I2C Block Diagram
4.7.3 I2C Bit Transfer
The data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW
state of the data line can only change when the clock signal on the SCL line is LOW. The exceptions
are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line
is high.
PS029502-0212
PRELIMINARY
112