Z51F0410 Datasheet, PDF (116/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
SDA
SCL
Data line Stable:
Data valid
exept S, Sr, P
Change of Data
allowed
Figure 4.28 Bit Transfer on the I2C-Bus
4.7.4 START / REPEATED START / STOP
One master can issue a START (S) condition to notice other devices connected to the SCL, SDA
lines that it will use the bus. A STOP (P) condition is generated by the master to release the bus lines
so that other devices can use it.
A high to low transition on the SDA line while SCL is high defines a START (S) condition.
A low to high transition on the SDA line while SCL is high defines a STOP (P) condition.
START and STOP conditions are always generated by the master. The bus is considered to be
busy after START condition. The bus is considered to be free again after STOP condition, ie, the bus
is busy between START and STOP condition. If a repeated START condition (Sr) is generated
instead of STOP condition, the bus stays busy. So, the START and repeated START conditions are
functionally identical.
SDA
SCL
S
START Condition
P
STOP Condition
4.7.5 DATA TRANSFER
Figure 4.29 START and STOP Condition
Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted
per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with
the most significant bit (MSB) first. If a slave can’t receive or transmit another complete byte of data
until it has performed some other function, it can hold the clock line SCL LOW to force the master into
a wait state. Data transfer then continues when the slave is ready for another byte of data and
releases clock line SCL.
PS029502-0212
PRELIMINARY
113