Z51F0410 Datasheet, PDF (55/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
enabled P0[7:0] pin toggles. The P0PC Register control which pins contribute to the pin change
interrupts.
2.3.2.7 Pin Mux Control Register (PINMCR)
In the 10pin PKG, The secondary pin muxing function is added for pin efficiency.
2.3.2.8 Pin PAD Data Register (P0PD)
It is used to read directly PAD data regardless of port direction.
2.3.2.9 PORT Selection Register0(PSR0, PSR1)
ADC Channel Selection (PSR0), and Comparator Output Selection (PSR1) disables the logic input
gate to prevent the leakage current.
2.3.2.10 Register Map
Name
P0
P0IO
P0PU
P0OD
P0DB
P0PC
P0PD
PINMCR
Address
80H
98H
89H
A1H
C0H
C1H
88H
92H
Table 2.3 Register map
Dir
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
00H
00H
00H
00H
00H
00H
00H
00H
Description
P0 Data Register
P0 Direction Register
P0 Pull-up Resistor Selection Register
P0 Open-drain Selection Register
P0 Debounce Enable Register
P0 Pin Change Interrupt Enable Register
P0 PAD Data Register
Pin Mux Control Register
2.3.3 P0 Port
2.3.3.1 P0 Port Description
P0 is 8-bit I/O port. P0 control registers consist of Data register (P0), direction register (P0IO),
debounce enable register (P0DB, P2DB), pull-up register selection register (P0PU), open-drain
selection register (P0OD).
2.3.3.2 Register description for P0
P0 (P0 Data Register) : 80H
7
6
5
4
3
2
1
0
P07
P06
P05
P04
P03
P02
P01
P00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PS029502-0212
PRELIMINARY
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