Z51F0410 Datasheet, PDF (62/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
3.4 Interrupt Vector Table
The interrupt controller supports 24 interrupt sources as shown in the Table 3.2 below. When
interrupt becomes service, long call instruction (LCALL) is executed in the vector address. Interrupt
request 24 has a decided priority order.
Table 3.2 Interrupt Vector Address Table
Interrupt Source
Symbol
Interrupt
Enable Bit
Polarity
Mask
Vector Address
Hardware Reset
-
External Interrupt 0
External Interrupt 1
-
-
Pin Change Interrupt (P0)
-
-
-
UART Rx
UART Tx
-
I2C
T0
T1
-
-
T4
ADC
Analog Comparator
WT
WDT
BIT
EEPROM
RESETB
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
INT12
INT13
INT14
INT15
INT16
INT17
INT18
INT19
INT20
INT21
INT22
INT23
0
IE0.0
IE0.1
IE0.2
IE0.3
IE0.4
IE0.5
IE1.0
IE1.1
IE1.2
IE1.3
IE1.4
IE1.5
IE2.0
IE2.1
IE2.2
IE2.3
IE2.4
IE2.5
IE3.0
IE3.1
IE3.2
IE3.3
IE3.4
IE3.5
0
NonMaskable
1
Maskable
2
Maskable
3
Maskable
4
Maskable
5
Maskable
6
Maskable
7
Maskable
8
Maskable
9
Maskable
10
Maskable
11
Maskable
12
Maskable
13
Maskable
14
Maskable
15
Maskable
16
Maskable
17
Maskable
18
Maskable
19
Maskable
20
Maskable
21
Maskable
22
Maskable
23
Maskable
24
Maskable
0000H
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
004BH
0053H
005BH
0063H
006BH
0073H
007BH
0083H
008BH
0093H
009BH
00A3H
00ABH
00B3H
00BBH
For maskable interrupt execution, first EA bit must set ‘1’ and specific interrupt source must set ‘1’ by
writing a ‘1’ to associated bit in the IEx. If interrupt request is received, specific interrupt request flag
set ‘1’. And it remains ‘1’ until CPU accepts interrupt. After that, interrupt request flag will be cleared
automatically.
3.5 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a
reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So
instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the
PC stack. For the interrupt service routine, the interrupt controller gives the address of LJMP
instruction to CPU. After finishing the current instruction, at the next instruction to go interrupt service
routine needs 3–9 machine cycle and the interrupt service task is terminated upon execution of an
interrupt return instruction [RETI]. After generating interrupt, to go to interrupt service routine, the
following process is progressed
PS029502-0212
PRELIMINARY
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